PC66 synchronous dynamic RAM (PC66 SDRAM)

In SDRAM technology, a clock signal is used to synchronize the input and output signals. The clock signal, which is coordinated with the CPU clock, guarantees that the central processing unit (CPU) and Synchronous Dynamic RAM (SDRAM) operate synchronously.

Since the central processing unit receives the data at a fixed time, it is also available for other operations in the meantime. Due to the clock rate, extremely fast, successive write and read operations can be performed using FPM DARMs and EDO DRAMs. Since the clock rate is the decisive parameter for the speed, the SDRAM DIMM modules are specified in MHz: So PC66 has 66 MHz, PC100 has 100 MHz, etc.

The PC66 has 168 pins, a burst cycle of 5-1-1 and is supplied with a supply voltage of 3.3 V (3V3).