virtual instruction set computing (VISC)

Virtual Instruction Set Computing (VISC) is a processor design from Soft Machines that was first introduced at the 2014 Linley Processor Conference in Santa Clara. With VISC, multi-core processors with four or more virtual cores jointly process a thread in x86 and ARM code to increase the number of instructions per cycle( IPC) processed. The ARM-32 or x86 instructions are optimized on a VISC instruction set at runtime.

The hardware design of a VISC processor consists of a front-end, a cache, and two or more physical cores whose Level 2( L2) cache provides backup for the cores' central cache and data caches. The front-end transmits instructions as sequences to the physical cores for processing. A software layer translates standard instructions into executable VISC instructions.

The approach of having multiple cores work on one thread was patented by AMD in 2003. Intel and IBM have also already worked on the use of multiple channels, as has Transmeta with the Crusoe chip. Since the performance gain decreases proportionally with an increasing number of cores, four cores are currently the realistic upper limit of the overall system.