three-dimensional integrated circuit (3D-IC)
The goal of many chip developments is the production of increasingly compact, space-saving packages with the smallest footprint. This development continues in the three-dimensional integrated circuits, the 3D ICs.
To achieve the most compact IC packages possible with short interconnect paths and optimum space utilization, separate chips are arranged next to or on top of each other in 3D ICs in a stacked design, as in the multi-chip module( MCM) or package-on-package( PoP), and encapsulated in a package. The individual chips of a 3D chip can realize the same or different functions, they can communicate with each other via buses or are interconnected via through- silicon vias( TSV). The technology used for 3D ICs is also known as System in Package( SiP).
The techniques used for manufacturing 3D ICs can be monolithic, they can be based on two and more wafers and include dice. In the monolithic technique, the electronic components are built up layer by layer on one wafer. This is then cut into dice. Since it is monolithic, there is no need to align the layers, as well as multiple bonding.
Due to its high compactness, the monolithic design has the disadvantage of limited heat dissipation. The situation is different with wafer-based construction methods. In this construction method, several wafers are placed on top of each other, aligned, bonded and cut into 3D ICs. The individual layers are bonded together using silicon vias or wire bonds. In a similar construction method, ready-cut dice can be combined with wafers or with each other, i.e. dice with dice.