A sample and hold (S/H) circuit is an electronic circuit connected upstream of an A/D converter. The sample and hold circuit samples the analog signal to be digitized later by taking a voltage sample (Sample), and holds the sampled voltage value for a certain period of time (Hold).
Function of the sample-and-hold circuit
The sample-and-hold circuit takes signal samples from the analog input signal at periodic intervals. From the circuit structure it is a low impedance switch, which is switched by a clock signal and realized by an active electronic component. This can be a transistor, field effect transistor( FET) or operational amplifier( OpAmp).
The switching element is low impedance only during the sampling time (Ts), and then high impedance during the hold time( TH). This prevents the charge from flowing out of the hold circuit, which is implemented by a charging capacitor. During each sample, the voltage sample to the charging capacitor is switched through during the sampling time. While the sampling time is relatively short, the hold time is correspondingly long.
The hold element is a high quality capacitor that temporarily stores the voltage sample for a short time. The buffering is necessary because the downstream A/D converters need time to quantize in order to encode a digital value from the buffered voltage. To prevent the capacitor charge from flowing away, known as droop, a buffer amplifier is placed between the hold circuit and the digitizing circuit.
Sample-and-hold circuits are characterized by their minimum switching times and the rise times of the clock pulses. In addition, the charging capacitor must hold the voltage value once stored for as long as possible without drift.