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reduced instruction set computer (RISC)

The RISC architecture, Reduced Instruction Set Computer (RISC), is a processor architecture that is characterized by the fact that the processor instructions are hard-wired into the chip.

This architecture allows the instructions to be called directly. The instruction structures are greatly reduced, which leads to a significant shortening of the computing operations, since no microprogram has to be loaded for processing. This is also expressed in the reduced computing time compared to Complex Instruction Set Computer( CISC).

RISC processors, such as the SPARC or the ARM processors, have a small instruction set; all instructions are usually executed in one clock cycle, whereas other processor architectures require from a few to over a hundred clock cycles to process an instruction.

In various CISC microprocessors, parts are implemented in RISC.

Informations:
Englisch: reduced instruction set computer - RISC
Updated at: 11.03.2008
#Words: 128
Links: architecture, processor, fact, chip, instruction
Translations: DE
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