powerWise interface (power management) (PWI)
PowerWise Interface (PWI) is a bus system, comparable to I2C, the Serial Peripheral Interface ( SPI) and the System Management Bus( SMBus), developed by ARM and National Semiconductor in collaboration with well-known companies in the entertainment and mobile device industries and established as an open standard for processor power management. The PWI bus uses active, efficient power management, Adaptive Voltage Scaling( AVS), and supports point-to-point and multipoint connections.
The PWI bus is a two- wire bus consisting of several hardware components such as the Hardware PerformanceMonitor( HPM) and Advanced Power Controller( APC) embedded in processors, Application Specific Integrated Circuit ( ASIC) or System-on-Chips( SoC) that perform control depending on the application and temperature profile. In addition to these two units, there is the Energy Management Unit( EMU), a standalone unit that provides optimal supply voltages. The Advanced Power Controllers and the Energy Management Unit communicate with each other.
The PWI bus operates in real-timemaster- slave mode. The PWI specifications define the functionalities of the PWI slaves, their operating states, the physical interface, the register and command sets, and the transmission protocol for notifications between the PWI master and PWI slaves. The first PWI version 1.0 was a point-to-point interface, while PWI 2.0 defines two PWI masters and up to 16 PWI slaves as a multipoint interface.