packaging

In the manufacture of assembled integrated circuits, the die chip, i.e. the chip core, is surrounded by a protective package and connected to the terminal contacts. This process is called packaging: placing the die chip with its contact terminals in a protective package.

During packaging, the chip is bonded to the underlying substrate, and the bond pads or bumps of the chips are bonded to the contact pads on the substrate. The protective package is slipped over this. The package protects the die against damage and corrosion and ensures that the power dissipation that occurs can be dissipated. Therefore, many packages are made of thermally conductive metals or ceramics and may be filled with a thermally conductive gel on the inside. Simpler packages are made of plastic.

Packaging can be performed as a stand-alone process, but it can also be performed directly during wafer fabrication. During packaging, the bonding, package size, type, number, position and spacing of the contact terminals, among other factors, play a decisive role. For many mobile devices, the packages must be as small as possible and should only take up a small amount of space. Therefore, Chip Scale Package( SCP) and Wafer Level Package(WLP) techniques have been developed where the package size is only slightly larger than the chip size.

Other techniques to reduce the package size are the through-silicon via( TSV) and the redistribution layer ( RDL).