Multi Level Cell (MLC) is a design form of flash memory. In contrast to Single Level Cells( SLC), which store 1 bit in a memory cell, Multi Level Cells store 2 bits per memory cell and Triple Level Cells store 3 bits and have a much higher storage density compared to Single Level Cells. Multi Level Cells and Triple Level Cells( TLC) operate with multiple discrete charge levels of the floating gate. MLC technology is used in NAND flashes, among other applications.
Since four different charge levels must be distinguished in a single transistor for 2 bits in an MLC device, the control of the charge levels must be exact. A four- level MLC cell can distinguish four different states: 00, 01, 10, and 11.
The 00 state represents fully programmed, 01 represents partially programmed, 10 represents partially erased, and 11 represents completely erased. For a Triple Level Cell (TLC), which can store three bits of information, eight different charge levels must be maintained. The exact state of charge and its readout are extremely critical and require precise read circuits. A further development is the Quadruple Level Cell( QLC), which operates with sixteen different charge levels and can store sixteen different binary states.
The high effort required to read the exact charge level reduces the write and read speed, and the error rate also increases. For this reason, MLC devices work with error correction methods such as the BCH code(Bose-Chaudhuri-Hocquenghem code), named after its developers R. C. Bose, D. K. Chaudhuri and A. Hocquenghem. The BCH code is especially suitable for error correction of multiple 1-bit errors in longer data words. MLC cells are slower than single level cells and have much fewer write cycles: about 3,000 to 10,000 instead of 100,000 of single level cells (SLC). This disadvantage could be compensated with eMLC technology (Enterprise). eMLC cells bring it to 20,000 to 30,000 write cycles.