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microprocessor without interlocked pipeline stages (MIPS)

The MIPS processor has a superscalar processor architecture and processes instructions within a clock pulse, as far as possible without pauses in the instruction cycle. Developed in the 1980s, the MIPS processor is used in embedded systems as well as in small and communication devices and also in workstations

. MIPS processors have a multi-stage instruction cycle and can process multiple instructions simultaneously. The development of MIPS processors began in 19985 with the R2000, followed by the R3000, which featured

anL1 cache for data and instructions and supported Symmetric Multiprocessing (SMP). The R4000 that followed in 1991 was a 64-bit CPU, it had a floating point unit (FPU) and a cache of 8 KB.

Further developments with the R4400 and the R5000 are more powerful than its predecessor and support graphics. With the R8000 a kind of dual core processor

is developed, which is superscalar and consists of two R4000. In the following MIPS CPUs, the R10000, R12000, R14000 and R16000, the arithmetic units, floating point units and caches are expanded and the clock speed

isincreased to over 1 GHz

. For example, the R10000 can simultaneously load four instructions from the instruction register, predictions for program branches are supported and logged by a counter. The R10000 operates with five functional units consisting of an address adder, two arithmetic units, a floating-point unit, and a floating-point adder.

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Englisch: microprocessor without interlocked pipeline stages - MIPS
Updated at: 24.03.2006
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