microprocessor without interlocked pipeline stages (MIPS)

The MIPS processor has a superscalar processor architecture and processes instructions within one clock pulse as far as possible without pauses in the instruction cycle. Developed in the 1980s, the MIPS processor is used in embedded systems as well as in small and communication devices and also in workstations. MIPS processors have a multi-stage instruction cycle and can process multiple instructions simultaneously.

MIPS processor development began in 19985 with the R2000, followed by the R3000, which featured an L1 cache for data and instructions and supported Symmetric Multiprocessing( SMP). The R4000 that followed in 1991 was a 64-bit CPU, it had a floating point unit( FPU) and a cache of 8 KB.

The further developments with the R4400 and the R5000 are more powerful than the predecessor and support graphics. With the R8000, a kind of dual-core processor is developed that is superscalar and consists of two R4000s. In the following MIPS CPUs, the R10000, R12000, R14000 and R16000, the arithmeticunits, floating point units and caches are expanded and the clock rate is increased to over 1 GHz.

For example, the R10000 can simultaneously load four instructions from the instruction register, and predictions for program branches are supported and logged by a counter. The R10000 operates with five functional units consisting of an address adder, two arithmetic units, a floating-point unit and a floating-point adder.