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memory controller hub (MCH)

Intel uses the shared CPU bus concept for various central processing units, in which a central Memory ControllerHub

(MCH) addresses the memories and peripherals. The Memory Controller Hub (MCH) corresponds to the Northbridge and is directly connected to the Front Side Bus (FSB). It controls the communication of the bus systems with the central processing units and controls the memories. It can also take over error correction (ECC) and eliminate bit errors on the frontside bus using appropriate procedures.

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Englisch: memory controller hub - MCH
Updated at: 03.10.2009
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