The Front Side Bus (FSB) is the interface for data transfer between the central processing unit( CPU) and the motherboard. The clock rate of the FSB is generally 100 MHz or 133 MHz, formerly also 33 MHz and 66 MHz. The CPU clock and the clock frequency for the buses or interfaces are derived from this clock frequency.
Various transfer methods have been developed to increase the data transfer rate between the central processing unit and the chipset. For example, Single Data Rate( SDR) transfers one data packet per clock pulse, Double Data Rate( DDR) doubles the data transfer rate by transferring two data pack ets with each clock pulse and Quad Data Rate( QDR) even four.
The transfer performance of the FSB must be adapted to the performance of the internal CPU bus and determines the maximum data transfer rate. This is calculated by multiplying the FSB clock rate by the data word width and the number of packets per clock cycle. This results, for example, in a data transfer rate of 800 MB/s with an FSB clock rate of 100 MHz, a bus width of 64 bits and one data packet per clock cycle. The calculated value applies to the Pentium II, for example.
In order to be able to use the data transfer rate optimally, other system components of the motherboard, such as the RAM, must be adapted to the performance of the FSB. To increase CPU efficiency, the clock rates of FSB buses are continuously increasing. For example, the clock rate of the Pentium-M successor is increased from 533 MHz to 667 MHz.
Due to CPU architectures in which the memory controllers are located in the central processing unit (CPU), the classic front side bus has lost its credentials.