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floating multiply-add (FMADD)

Floating Multiply-Add (FMADD) is a combined command for central processing units in which two mathematical operations

are combined: multiplication and addition. This command combination is specified by the manufacturers to determine

thecomputing power

. The combined FMADD instruction is includedin the floating point operations per second

(FLOPS) performance calculation, but as if it were two separate operations. A 64-bit operation can be performed at dual precision with a combined FMADD instruction in one clock cycle. Such an operation could also be executed with single precision, but it would then require four clocks.

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Englisch: floating multiply-add - FMADD
Updated at: 16.09.2010
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