The basic structure of the PCI Express standardized by the PCI Special Interest Group (PCI- SIG) consists of one lane with two differential line pairs, one for sending, the other for receiving data. A PCI Express bus can consist of up to 32 lanes, which can be bundled together to increase the data transfer rate. The data is transmitted as differential signals with a clock frequency of 1.25 GHz. As a result, up to 2.5 Gbit/s can be transmitted bidirectionally, which corresponds to a data transfer rate of 250 MB/s per line pair and 500 MB/s per lane.
A further increase in data transfer rates is possible by bundling several lanes. With two lanes, PCI2 2.0 x2 achieves a data rate of 10 Gbit/s and with 8B/10B coding, a data transfer rate of about 8 GB/s. With four lanes, these values double. With PCIe 3.0 x2, i.e. two lanes, 16 Gbit/s are achieved and a transfer rate of 1.25 GB/s and with four lanes 32 Gbit/s and 2.5 GB/s respectively.
With the bundling of 32 lanes, transfer rates of 2 x 8 GB/s are achieved. This PCIe x16 version is also called PCI Express for Graphics( PEG) and is implemented in version 3.0. It is intended to support broadband systems with high-end graphics chips, 100 Gigabit Ethernet or Fibre Channel cards.
The transmission method has been optimized for FR4 PCB material and allows a maximum length of 50 cm. The connection technology is relatively uncritical, since the PCI Express derives the clock signal from the data signal. The PCI-Express has a cyclic block check(CRC) for error correction and operates DC-free with 8B/10B coding. In the 8 GB/s version, the 8B/10B coding is replaced by 128B/130B coding, since this has a much lower offset of only 1.6%.
In desktops, PCI Express is also used as a graphics card interface. For notebooks, Mini-PCI-Express( MiniPCIe) is a card version in miniature format that replaces the Mini-PCI cards. It has a contact strip with a notch and 52 contacts, a width of 30 mm and various installation depths. of 51 mm and a thickness of only 5 mm.