IEEE 1149
The traditional measurement technique can no longer be used on extremely compactly assembled PCBs and on chips because the probes cannot contact the circuit points. In addition, the probes would stress the circuit and change data rates, cause clock delays or timing problems, and thus falsify the measured values.
For these reasons, IEEE 1149 working groups relied on embedded technologies such as embedded instruments with on- chip measurement technology. Here, the measurement and test procedures are embedded on the chips, printed circuit boards or in the buses. IEEE 1149 provides a standardized interface for emulation, programming and debugging of microcontrollers. Physically, the interface is implemented with connectors such as the JTAG connector or the ISP(In-System Programming) connector.
The first standards for embedded measurement technology were developed in the early 1990s by the IEEE 1149.1 working group with boundary scan. This was the first time that parts of the test equipment were built directly into the chips. Later, a test for high-speed buses was developed with the IEEE 1149.6 standard. IEEE 1149.6 is a further development of 1149.1. In contrast to 1149.1, which works with DC voltage levels, the bondary scan according to 1149.6 works with differential signals for AC voltage-coupled circuits.
The 1149 standards:
IEEE 1149.1: Standard Test Access Port and Boundary Scan Architecture, Static digital bond test for digital boards. The IEEE 1149.1 test has been improved in several revisions; it is limited to digital circuits. The test access allows implementation with today's design. It supports many test and debug applications and some applications that were not envisioned at the time the standard was developed. It is suitable for testing digital boards with central processing units( CPU) or microprocessors (µP), digital signal processors( DSP), programmable logic devices( PLD), and field programmable gate arrays( FPGA)
IEEE 1149.4: Standard for a Mixed Signal Test Bus. Analog device test and analog interconnect and parameter test. EEE 1149.4 compliant devices have the two additional test bus signals AT1 and AT2. These two test bus signals can be connected to I/O pins via a switching structure for test purposes. Typically, they are used to supply a constant current to one pin and measure the voltage on that pin and another pin. This test approach is used to measure resistance and capacitance in the circuit
IEEE 1149.6: Dynamic digital interconnect test, for example for Low Voltage Differential Signaling( LVDS) and PCI Express.
To solve the problem of serially connected capacitors in a signal path and to enable boundary scan tests in it, an IEEE working group defined IEEE Standard 1149.6 in 2003. This standard for boundary scan tests of advanced digital networks is based on the transmission of signal transitions and not on static logical high and logical low levels.
IEEE 1149.7: The Mobile Industry Processor Interface( MIPI) Test and Debug Working Group has selected a new test and debug interface called Compact JTAG (cJTAG) that builds on the IEEE1149.1 standard. The goal of cJTAG, proposed as IEEE standard P1149.7, is to enable advances in test and debug functionality by creating a superset of the IEEE 1149.1 test interface while maintaining compatibility with IEEE 1149.1. A key goal of cJTAG was to preserve the industry's hardware and software investment in this standard. With cJTAG, existing tools or debug and test systems( DTS), such as an IEEE 1149.1 emulator and target system( TS) chips, can be easily extended with adapters to migrate to the cJTAG interface.